circuit MyMMU :
  module MYFIFO :
    input clock : Clock
    input reset : Reset
    output io : { flip memData : UInt<512>, flip memValid : UInt<1>, flip advance_fifo : UInt<1>, tile : UInt<24>[3], ready : UInt<1>, full : UInt<1>}

    reg state : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MYFIFO.scala 33:28]
    reg startup : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MYFIFO.scala 34:30]
    startup <= UInt<1>("h1") @[MYFIFO.scala 34:30]
    wire _topBuf_WIRE : UInt<512>[1] @[MYFIFO.scala 38:37]
    _topBuf_WIRE[0] <= UInt<512>("h0") @[MYFIFO.scala 38:37]
    reg topBuf : UInt<512>[1], clock with :
      reset => (reset, _topBuf_WIRE) @[MYFIFO.scala 38:29]
    reg droptile : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MYFIFO.scala 41:31]
    wire clearDrop : UInt<1>
    clearDrop <= UInt<1>("h0")
    when io.advance_fifo : @[MYFIFO.scala 44:30]
      droptile <= UInt<1>("h1") @[MYFIFO.scala 45:26]
    else :
      when clearDrop : @[MYFIFO.scala 46:32]
        droptile <= UInt<1>("h0") @[MYFIFO.scala 47:26]
    when io.memValid : @[MYFIFO.scala 51:26]
      node _T = lt(state, UInt<1>("h0")) @[MYFIFO.scala 52:27]
      when _T : @[MYFIFO.scala 52:41]
        node _state_T = add(state, UInt<1>("h1")) @[MYFIFO.scala 53:40]
        node _state_T_1 = tail(_state_T, 1) @[MYFIFO.scala 53:40]
        state <= _state_T_1 @[MYFIFO.scala 53:31]
      else :
        state <= UInt<1>("h0") @[MYFIFO.scala 55:31]
      topBuf[UInt<1>("h0")] <= io.memData @[MYFIFO.scala 58:31]
    reg full : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MYFIFO.scala 62:27]
    wire clearTop : UInt<1>
    clearTop <= UInt<1>("h0")
    node _T_1 = eq(state, UInt<1>("h0")) @[MYFIFO.scala 64:35]
    node _T_2 = and(io.memValid, _T_1) @[MYFIFO.scala 64:26]
    when _T_2 : @[MYFIFO.scala 64:52]
      full <= UInt<1>("h1") @[MYFIFO.scala 65:22]
    else :
      when clearTop : @[MYFIFO.scala 66:31]
        full <= UInt<1>("h0") @[MYFIFO.scala 67:22]
    reg buf2 : UInt<72>, clock with :
      reset => (reset, UInt<72>("h0")) @[MYFIFO.scala 71:27]
    reg buf3 : UInt<72>, clock with :
      reset => (reset, UInt<72>("h0")) @[MYFIFO.scala 72:27]
    reg buf4 : UInt<72>, clock with :
      reset => (reset, UInt<72>("h0")) @[MYFIFO.scala 73:27]
    reg empty2 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h1")) @[MYFIFO.scala 75:29]
    reg empty3 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h1")) @[MYFIFO.scala 76:29]
    reg empty4 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h1")) @[MYFIFO.scala 77:29]
    node _T_3 = not(startup) @[MYFIFO.scala 79:14]
    when _T_3 : @[MYFIFO.scala 79:23]
      empty2 <= UInt<1>("h1") @[MYFIFO.scala 80:24]
      empty3 <= UInt<1>("h1") @[MYFIFO.scala 81:24]
      empty4 <= UInt<1>("h1") @[MYFIFO.scala 82:24]
    else :
      node _T_4 = and(full, empty2) @[MYFIFO.scala 83:26]
      when _T_4 : @[MYFIFO.scala 83:37]
        buf2 <= topBuf[0] @[MYFIFO.scala 84:22]
        clearTop <= UInt<1>("h1") @[MYFIFO.scala 85:26]
        empty2 <= UInt<1>("h0") @[MYFIFO.scala 86:24]
      else :
        node _T_5 = not(empty2) @[MYFIFO.scala 87:31]
        node _T_6 = and(empty3, _T_5) @[MYFIFO.scala 87:28]
        when _T_6 : @[MYFIFO.scala 87:39]
          buf3 <= buf2 @[MYFIFO.scala 88:22]
          empty3 <= UInt<1>("h0") @[MYFIFO.scala 89:24]
          empty2 <= UInt<1>("h1") @[MYFIFO.scala 90:24]
        else :
          node _T_7 = not(empty3) @[MYFIFO.scala 91:31]
          node _T_8 = and(empty4, _T_7) @[MYFIFO.scala 91:28]
          when _T_8 : @[MYFIFO.scala 91:39]
            buf4 <= buf3 @[MYFIFO.scala 92:22]
            empty4 <= UInt<1>("h0") @[MYFIFO.scala 93:24]
            empty3 <= UInt<1>("h1") @[MYFIFO.scala 94:24]
          else :
            when droptile : @[MYFIFO.scala 95:30]
              empty4 <= UInt<1>("h1") @[MYFIFO.scala 96:24]
              clearDrop <= UInt<1>("h1") @[MYFIFO.scala 97:27]
    node _io_ready_T = not(empty4) @[MYFIFO.scala 100:33]
    node _io_ready_T_1 = and(startup, _io_ready_T) @[MYFIFO.scala 100:29]
    node _io_ready_T_2 = not(droptile) @[MYFIFO.scala 100:46]
    node _io_ready_T_3 = and(_io_ready_T_1, _io_ready_T_2) @[MYFIFO.scala 100:42]
    io.ready <= _io_ready_T_3 @[MYFIFO.scala 100:18]
    io.full <= full @[MYFIFO.scala 101:17]
    node _io_tile_0_T = bits(buf4, 23, 0) @[MYFIFO.scala 103:35]
    io.tile[0] <= _io_tile_0_T @[MYFIFO.scala 103:28]
    node _io_tile_1_T = bits(buf4, 47, 24) @[MYFIFO.scala 103:35]
    io.tile[1] <= _io_tile_1_T @[MYFIFO.scala 103:28]
    node _io_tile_2_T = bits(buf4, 71, 48) @[MYFIFO.scala 103:35]
    io.tile[2] <= _io_tile_2_T @[MYFIFO.scala 103:28]

  module MACArraySetUp :
    input clock : Clock
    input reset : Reset
    output io : { flip dataIn : UInt<72>, mmu2setup : { flip waddr : UInt<8>, flip wen : UInt<1>, flip wclear : UInt<1>, flip lastvec : UInt<1>}, flip switch : UInt<1>, nextRow : SInt<8>[3], switchOut : UInt<1>[3], flip setup2accu : { flip waddr : UInt<8>, flip wen : UInt<1>, flip wclear : UInt<1>, flip lastvec : UInt<1>}}

    wire _firstColumnReg_WIRE : UInt<8>[3] @[macarraySetup.scala 23:45]
    _firstColumnReg_WIRE[0] <= UInt<8>("h0") @[macarraySetup.scala 23:45]
    _firstColumnReg_WIRE[1] <= UInt<8>("h0") @[macarraySetup.scala 23:45]
    _firstColumnReg_WIRE[2] <= UInt<8>("h0") @[macarraySetup.scala 23:45]
    reg firstColumnReg : UInt<8>[3], clock with :
      reset => (reset, _firstColumnReg_WIRE) @[macarraySetup.scala 23:37]
    node _firstColumnReg_0_T = bits(io.dataIn, 7, 0) @[macarraySetup.scala 29:47]
    firstColumnReg[0] <= _firstColumnReg_0_T @[macarraySetup.scala 29:35]
    node _firstColumnReg_1_T = bits(io.dataIn, 15, 8) @[macarraySetup.scala 29:47]
    firstColumnReg[1] <= _firstColumnReg_1_T @[macarraySetup.scala 29:35]
    node _firstColumnReg_2_T = bits(io.dataIn, 23, 16) @[macarraySetup.scala 29:47]
    firstColumnReg[2] <= _firstColumnReg_2_T @[macarraySetup.scala 29:35]
    wire diagnonalWire : UInt<8>[3] @[macarraySetup.scala 33:33]
    wire _switchReg_WIRE : UInt<1>[3] @[macarraySetup.scala 36:40]
    _switchReg_WIRE[0] <= UInt<1>("h0") @[macarraySetup.scala 36:40]
    _switchReg_WIRE[1] <= UInt<1>("h0") @[macarraySetup.scala 36:40]
    _switchReg_WIRE[2] <= UInt<1>("h0") @[macarraySetup.scala 36:40]
    reg switchReg : UInt<1>[3], clock with :
      reset => (reset, _switchReg_WIRE) @[macarraySetup.scala 36:32]
    switchReg[0] <= switchReg[1] @[macarraySetup.scala 45:32]
    switchReg[1] <= switchReg[2] @[macarraySetup.scala 45:32]
    switchReg[2] <= io.switch @[macarraySetup.scala 47:24]
    reg io_setup2accu_waddr_r : UInt<8>, clock with :
      reset => (reset, UInt<8>("h0")) @[Reg.scala 28:20]
    when UInt<1>("h1") : @[Reg.scala 29:18]
      io_setup2accu_waddr_r <= io.mmu2setup.waddr @[Reg.scala 29:22]
    reg io_setup2accu_waddr_r_1 : UInt<8>, clock with :
      reset => (reset, UInt<8>("h0")) @[Reg.scala 28:20]
    when UInt<1>("h1") : @[Reg.scala 29:18]
      io_setup2accu_waddr_r_1 <= io_setup2accu_waddr_r @[Reg.scala 29:22]
    reg io_setup2accu_waddr_r_2 : UInt<8>, clock with :
      reset => (reset, UInt<8>("h0")) @[Reg.scala 28:20]
    when UInt<1>("h1") : @[Reg.scala 29:18]
      io_setup2accu_waddr_r_2 <= io_setup2accu_waddr_r_1 @[Reg.scala 29:22]
    reg io_setup2accu_waddr_r_3 : UInt<8>, clock with :
      reset => (reset, UInt<8>("h0")) @[Reg.scala 28:20]
    when UInt<1>("h1") : @[Reg.scala 29:18]
      io_setup2accu_waddr_r_3 <= io_setup2accu_waddr_r_2 @[Reg.scala 29:22]
    io.setup2accu.waddr <= io_setup2accu_waddr_r_3 @[macarraySetup.scala 51:29]
    reg io_setup2accu_wen_r : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Reg.scala 28:20]
    when UInt<1>("h1") : @[Reg.scala 29:18]
      io_setup2accu_wen_r <= io.mmu2setup.wen @[Reg.scala 29:22]
    reg io_setup2accu_wen_r_1 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Reg.scala 28:20]
    when UInt<1>("h1") : @[Reg.scala 29:18]
      io_setup2accu_wen_r_1 <= io_setup2accu_wen_r @[Reg.scala 29:22]
    reg io_setup2accu_wen_r_2 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Reg.scala 28:20]
    when UInt<1>("h1") : @[Reg.scala 29:18]
      io_setup2accu_wen_r_2 <= io_setup2accu_wen_r_1 @[Reg.scala 29:22]
    reg io_setup2accu_wen_r_3 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Reg.scala 28:20]
    when UInt<1>("h1") : @[Reg.scala 29:18]
      io_setup2accu_wen_r_3 <= io_setup2accu_wen_r_2 @[Reg.scala 29:22]
    io.setup2accu.wen <= io_setup2accu_wen_r_3 @[macarraySetup.scala 52:27]
    reg io_setup2accu_wclear_r : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Reg.scala 28:20]
    when UInt<1>("h1") : @[Reg.scala 29:18]
      io_setup2accu_wclear_r <= io.mmu2setup.wclear @[Reg.scala 29:22]
    reg io_setup2accu_wclear_r_1 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Reg.scala 28:20]
    when UInt<1>("h1") : @[Reg.scala 29:18]
      io_setup2accu_wclear_r_1 <= io_setup2accu_wclear_r @[Reg.scala 29:22]
    reg io_setup2accu_wclear_r_2 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Reg.scala 28:20]
    when UInt<1>("h1") : @[Reg.scala 29:18]
      io_setup2accu_wclear_r_2 <= io_setup2accu_wclear_r_1 @[Reg.scala 29:22]
    reg io_setup2accu_wclear_r_3 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Reg.scala 28:20]
    when UInt<1>("h1") : @[Reg.scala 29:18]
      io_setup2accu_wclear_r_3 <= io_setup2accu_wclear_r_2 @[Reg.scala 29:22]
    io.setup2accu.wclear <= io_setup2accu_wclear_r_3 @[macarraySetup.scala 53:30]
    reg io_setup2accu_lastvec_r : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Reg.scala 28:20]
    when UInt<1>("h1") : @[Reg.scala 29:18]
      io_setup2accu_lastvec_r <= io.mmu2setup.lastvec @[Reg.scala 29:22]
    reg io_setup2accu_lastvec_r_1 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Reg.scala 28:20]
    when UInt<1>("h1") : @[Reg.scala 29:18]
      io_setup2accu_lastvec_r_1 <= io_setup2accu_lastvec_r @[Reg.scala 29:22]
    reg io_setup2accu_lastvec_r_2 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Reg.scala 28:20]
    when UInt<1>("h1") : @[Reg.scala 29:18]
      io_setup2accu_lastvec_r_2 <= io_setup2accu_lastvec_r_1 @[Reg.scala 29:22]
    io.setup2accu.lastvec <= io_setup2accu_lastvec_r_2 @[macarraySetup.scala 54:31]
    io.switchOut[0] <= switchReg[0] @[macarraySetup.scala 56:22]
    io.switchOut[1] <= switchReg[1] @[macarraySetup.scala 56:22]
    io.switchOut[2] <= switchReg[2] @[macarraySetup.scala 56:22]
    diagnonalWire[2] <= firstColumnReg[0] @[macarraySetup.scala 62:44]
    reg diagnonalWire_1_r : UInt<8>, clock with :
      reset => (UInt<1>("h0"), diagnonalWire_1_r) @[Reg.scala 16:16]
    when UInt<1>("h1") : @[Reg.scala 17:18]
      diagnonalWire_1_r <= firstColumnReg[1] @[Reg.scala 17:22]
    diagnonalWire[1] <= diagnonalWire_1_r @[macarraySetup.scala 62:44]
    reg diagnonalWire_0_r : UInt<8>, clock with :
      reset => (UInt<1>("h0"), diagnonalWire_0_r) @[Reg.scala 16:16]
    when UInt<1>("h1") : @[Reg.scala 17:18]
      diagnonalWire_0_r <= firstColumnReg[2] @[Reg.scala 17:22]
    reg diagnonalWire_0_r_1 : UInt<8>, clock with :
      reset => (UInt<1>("h0"), diagnonalWire_0_r_1) @[Reg.scala 16:16]
    when UInt<1>("h1") : @[Reg.scala 17:18]
      diagnonalWire_0_r_1 <= diagnonalWire_0_r @[Reg.scala 17:22]
    diagnonalWire[0] <= diagnonalWire_0_r_1 @[macarraySetup.scala 62:44]
    node _io_nextRow_0_T = asSInt(diagnonalWire[0]) @[macarraySetup.scala 65:51]
    io.nextRow[0] <= _io_nextRow_0_T @[macarraySetup.scala 65:31]
    node _io_nextRow_1_T = asSInt(diagnonalWire[1]) @[macarraySetup.scala 65:51]
    io.nextRow[1] <= _io_nextRow_1_T @[macarraySetup.scala 65:31]
    node _io_nextRow_2_T = asSInt(diagnonalWire[2]) @[macarraySetup.scala 65:51]
    io.nextRow[2] <= _io_nextRow_2_T @[macarraySetup.scala 65:31]

  module MYMAC :
    input clock : Clock
    input reset : Reset
    output io : { macIO : { flip dataIn : SInt<8>, flip accIn : SInt<32>, flip switchw : UInt<1>, flip weightIn : SInt<8>, flip weightWe : UInt<1>, flip weightTag : UInt<8>, outDelay : SInt, dataDelay : SInt, switchDelay : UInt<1>, weightDelay : SInt, weightWeDelay : UInt<1>, weightTagDelay : UInt}}

    reg wbuf1 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg wbuf2 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg currentBufferReg : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 46:33]
    when io.macIO.switchw : @[MAC.scala 47:25]
      node _currentBufferReg_T = not(currentBufferReg) @[MAC.scala 48:25]
      currentBufferReg <= _currentBufferReg_T @[MAC.scala 48:22]
    node currenBuffer = xor(currentBufferReg, io.macIO.switchw) @[MAC.scala 51:39]
    node _T = eq(io.macIO.weightTag, UInt<2>("h2")) @[MAC.scala 53:47]
    node _T_1 = and(io.macIO.weightWe, _T) @[MAC.scala 53:26]
    when _T_1 : @[MAC.scala 53:67]
      node _T_2 = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 54:22]
      when _T_2 : @[MAC.scala 54:29]
        wbuf2 <= io.macIO.weightIn @[MAC.scala 55:13]
      else :
        wbuf1 <= io.macIO.weightIn @[MAC.scala 57:13]
    node _weight_T = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 61:32]
    node weight = mux(_weight_T, wbuf2, wbuf1) @[MAC.scala 61:19]
    node product = mul(weight, io.macIO.dataIn) @[MAC.scala 62:24]
    node _out_T = add(product, io.macIO.accIn) @[MAC.scala 63:21]
    node _out_T_1 = tail(_out_T, 1) @[MAC.scala 63:21]
    node out = asSInt(_out_T_1) @[MAC.scala 63:21]
    reg io_macIO_dataDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 67:32]
    io_macIO_dataDelay_REG <= io.macIO.dataIn @[MAC.scala 67:32]
    io.macIO.dataDelay <= io_macIO_dataDelay_REG @[MAC.scala 67:22]
    reg io_macIO_switchDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 68:34]
    io_macIO_switchDelay_REG <= io.macIO.switchw @[MAC.scala 68:34]
    io.macIO.switchDelay <= io_macIO_switchDelay_REG @[MAC.scala 68:24]
    reg io_macIO_outDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 69:31]
    io_macIO_outDelay_REG <= out @[MAC.scala 69:31]
    io.macIO.outDelay <= io_macIO_outDelay_REG @[MAC.scala 69:21]
    reg io_macIO_weightDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 70:34]
    io_macIO_weightDelay_REG <= io.macIO.weightIn @[MAC.scala 70:34]
    io.macIO.weightDelay <= io_macIO_weightDelay_REG @[MAC.scala 70:24]
    reg io_macIO_weightWeDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 71:36]
    io_macIO_weightWeDelay_REG <= io.macIO.weightWe @[MAC.scala 71:36]
    io.macIO.weightWeDelay <= io_macIO_weightWeDelay_REG @[MAC.scala 71:26]
    node _io_macIO_weightTagDelay_T = add(io.macIO.weightTag, UInt<1>("h1")) @[MAC.scala 72:58]
    node _io_macIO_weightTagDelay_T_1 = tail(_io_macIO_weightTagDelay_T, 1) @[MAC.scala 72:58]
    reg io_macIO_weightTagDelay_REG : UInt, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 72:37]
    io_macIO_weightTagDelay_REG <= _io_macIO_weightTagDelay_T_1 @[MAC.scala 72:37]
    io.macIO.weightTagDelay <= io_macIO_weightTagDelay_REG @[MAC.scala 72:27]

  module MYMAC_1 :
    input clock : Clock
    input reset : Reset
    output io : { macIO : { flip dataIn : SInt<8>, flip accIn : SInt<32>, flip switchw : UInt<1>, flip weightIn : SInt<8>, flip weightWe : UInt<1>, flip weightTag : UInt<8>, outDelay : SInt, dataDelay : SInt, switchDelay : UInt<1>, weightDelay : SInt, weightWeDelay : UInt<1>, weightTagDelay : UInt}}

    reg wbuf1 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg wbuf2 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg currentBufferReg : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 46:33]
    when io.macIO.switchw : @[MAC.scala 47:25]
      node _currentBufferReg_T = not(currentBufferReg) @[MAC.scala 48:25]
      currentBufferReg <= _currentBufferReg_T @[MAC.scala 48:22]
    node currenBuffer = xor(currentBufferReg, io.macIO.switchw) @[MAC.scala 51:39]
    node _T = eq(io.macIO.weightTag, UInt<2>("h2")) @[MAC.scala 53:47]
    node _T_1 = and(io.macIO.weightWe, _T) @[MAC.scala 53:26]
    when _T_1 : @[MAC.scala 53:67]
      node _T_2 = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 54:22]
      when _T_2 : @[MAC.scala 54:29]
        wbuf2 <= io.macIO.weightIn @[MAC.scala 55:13]
      else :
        wbuf1 <= io.macIO.weightIn @[MAC.scala 57:13]
    node _weight_T = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 61:32]
    node weight = mux(_weight_T, wbuf2, wbuf1) @[MAC.scala 61:19]
    node product = mul(weight, io.macIO.dataIn) @[MAC.scala 62:24]
    node _out_T = add(product, io.macIO.accIn) @[MAC.scala 63:21]
    node _out_T_1 = tail(_out_T, 1) @[MAC.scala 63:21]
    node out = asSInt(_out_T_1) @[MAC.scala 63:21]
    reg io_macIO_dataDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 67:32]
    io_macIO_dataDelay_REG <= io.macIO.dataIn @[MAC.scala 67:32]
    io.macIO.dataDelay <= io_macIO_dataDelay_REG @[MAC.scala 67:22]
    reg io_macIO_switchDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 68:34]
    io_macIO_switchDelay_REG <= io.macIO.switchw @[MAC.scala 68:34]
    io.macIO.switchDelay <= io_macIO_switchDelay_REG @[MAC.scala 68:24]
    reg io_macIO_outDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 69:31]
    io_macIO_outDelay_REG <= out @[MAC.scala 69:31]
    io.macIO.outDelay <= io_macIO_outDelay_REG @[MAC.scala 69:21]
    reg io_macIO_weightDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 70:34]
    io_macIO_weightDelay_REG <= io.macIO.weightIn @[MAC.scala 70:34]
    io.macIO.weightDelay <= io_macIO_weightDelay_REG @[MAC.scala 70:24]
    reg io_macIO_weightWeDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 71:36]
    io_macIO_weightWeDelay_REG <= io.macIO.weightWe @[MAC.scala 71:36]
    io.macIO.weightWeDelay <= io_macIO_weightWeDelay_REG @[MAC.scala 71:26]
    node _io_macIO_weightTagDelay_T = add(io.macIO.weightTag, UInt<1>("h1")) @[MAC.scala 72:58]
    node _io_macIO_weightTagDelay_T_1 = tail(_io_macIO_weightTagDelay_T, 1) @[MAC.scala 72:58]
    reg io_macIO_weightTagDelay_REG : UInt, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 72:37]
    io_macIO_weightTagDelay_REG <= _io_macIO_weightTagDelay_T_1 @[MAC.scala 72:37]
    io.macIO.weightTagDelay <= io_macIO_weightTagDelay_REG @[MAC.scala 72:27]

  module MYMAC_2 :
    input clock : Clock
    input reset : Reset
    output io : { macIO : { flip dataIn : SInt<8>, flip accIn : SInt<32>, flip switchw : UInt<1>, flip weightIn : SInt<8>, flip weightWe : UInt<1>, flip weightTag : UInt<8>, outDelay : SInt, dataDelay : SInt, switchDelay : UInt<1>, weightDelay : SInt, weightWeDelay : UInt<1>, weightTagDelay : UInt}}

    reg wbuf1 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg wbuf2 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg currentBufferReg : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 46:33]
    when io.macIO.switchw : @[MAC.scala 47:25]
      node _currentBufferReg_T = not(currentBufferReg) @[MAC.scala 48:25]
      currentBufferReg <= _currentBufferReg_T @[MAC.scala 48:22]
    node currenBuffer = xor(currentBufferReg, io.macIO.switchw) @[MAC.scala 51:39]
    node _T = eq(io.macIO.weightTag, UInt<2>("h2")) @[MAC.scala 53:47]
    node _T_1 = and(io.macIO.weightWe, _T) @[MAC.scala 53:26]
    when _T_1 : @[MAC.scala 53:67]
      node _T_2 = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 54:22]
      when _T_2 : @[MAC.scala 54:29]
        wbuf2 <= io.macIO.weightIn @[MAC.scala 55:13]
      else :
        wbuf1 <= io.macIO.weightIn @[MAC.scala 57:13]
    node _weight_T = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 61:32]
    node weight = mux(_weight_T, wbuf2, wbuf1) @[MAC.scala 61:19]
    node product = mul(weight, io.macIO.dataIn) @[MAC.scala 62:24]
    node _out_T = add(product, io.macIO.accIn) @[MAC.scala 63:21]
    node _out_T_1 = tail(_out_T, 1) @[MAC.scala 63:21]
    node out = asSInt(_out_T_1) @[MAC.scala 63:21]
    reg io_macIO_dataDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 67:32]
    io_macIO_dataDelay_REG <= io.macIO.dataIn @[MAC.scala 67:32]
    io.macIO.dataDelay <= io_macIO_dataDelay_REG @[MAC.scala 67:22]
    reg io_macIO_switchDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 68:34]
    io_macIO_switchDelay_REG <= io.macIO.switchw @[MAC.scala 68:34]
    io.macIO.switchDelay <= io_macIO_switchDelay_REG @[MAC.scala 68:24]
    reg io_macIO_outDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 69:31]
    io_macIO_outDelay_REG <= out @[MAC.scala 69:31]
    io.macIO.outDelay <= io_macIO_outDelay_REG @[MAC.scala 69:21]
    reg io_macIO_weightDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 70:34]
    io_macIO_weightDelay_REG <= io.macIO.weightIn @[MAC.scala 70:34]
    io.macIO.weightDelay <= io_macIO_weightDelay_REG @[MAC.scala 70:24]
    reg io_macIO_weightWeDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 71:36]
    io_macIO_weightWeDelay_REG <= io.macIO.weightWe @[MAC.scala 71:36]
    io.macIO.weightWeDelay <= io_macIO_weightWeDelay_REG @[MAC.scala 71:26]
    node _io_macIO_weightTagDelay_T = add(io.macIO.weightTag, UInt<1>("h1")) @[MAC.scala 72:58]
    node _io_macIO_weightTagDelay_T_1 = tail(_io_macIO_weightTagDelay_T, 1) @[MAC.scala 72:58]
    reg io_macIO_weightTagDelay_REG : UInt, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 72:37]
    io_macIO_weightTagDelay_REG <= _io_macIO_weightTagDelay_T_1 @[MAC.scala 72:37]
    io.macIO.weightTagDelay <= io_macIO_weightTagDelay_REG @[MAC.scala 72:27]

  module MYMAC_3 :
    input clock : Clock
    input reset : Reset
    output io : { macIO : { flip dataIn : SInt<8>, flip accIn : SInt<32>, flip switchw : UInt<1>, flip weightIn : SInt<8>, flip weightWe : UInt<1>, flip weightTag : UInt<8>, outDelay : SInt, dataDelay : SInt, switchDelay : UInt<1>, weightDelay : SInt, weightWeDelay : UInt<1>, weightTagDelay : UInt}}

    reg wbuf1 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg wbuf2 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg currentBufferReg : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 46:33]
    when io.macIO.switchw : @[MAC.scala 47:25]
      node _currentBufferReg_T = not(currentBufferReg) @[MAC.scala 48:25]
      currentBufferReg <= _currentBufferReg_T @[MAC.scala 48:22]
    node currenBuffer = xor(currentBufferReg, io.macIO.switchw) @[MAC.scala 51:39]
    node _T = eq(io.macIO.weightTag, UInt<2>("h2")) @[MAC.scala 53:47]
    node _T_1 = and(io.macIO.weightWe, _T) @[MAC.scala 53:26]
    when _T_1 : @[MAC.scala 53:67]
      node _T_2 = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 54:22]
      when _T_2 : @[MAC.scala 54:29]
        wbuf2 <= io.macIO.weightIn @[MAC.scala 55:13]
      else :
        wbuf1 <= io.macIO.weightIn @[MAC.scala 57:13]
    node _weight_T = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 61:32]
    node weight = mux(_weight_T, wbuf2, wbuf1) @[MAC.scala 61:19]
    node product = mul(weight, io.macIO.dataIn) @[MAC.scala 62:24]
    node _out_T = add(product, io.macIO.accIn) @[MAC.scala 63:21]
    node _out_T_1 = tail(_out_T, 1) @[MAC.scala 63:21]
    node out = asSInt(_out_T_1) @[MAC.scala 63:21]
    reg io_macIO_dataDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 67:32]
    io_macIO_dataDelay_REG <= io.macIO.dataIn @[MAC.scala 67:32]
    io.macIO.dataDelay <= io_macIO_dataDelay_REG @[MAC.scala 67:22]
    reg io_macIO_switchDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 68:34]
    io_macIO_switchDelay_REG <= io.macIO.switchw @[MAC.scala 68:34]
    io.macIO.switchDelay <= io_macIO_switchDelay_REG @[MAC.scala 68:24]
    reg io_macIO_outDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 69:31]
    io_macIO_outDelay_REG <= out @[MAC.scala 69:31]
    io.macIO.outDelay <= io_macIO_outDelay_REG @[MAC.scala 69:21]
    reg io_macIO_weightDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 70:34]
    io_macIO_weightDelay_REG <= io.macIO.weightIn @[MAC.scala 70:34]
    io.macIO.weightDelay <= io_macIO_weightDelay_REG @[MAC.scala 70:24]
    reg io_macIO_weightWeDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 71:36]
    io_macIO_weightWeDelay_REG <= io.macIO.weightWe @[MAC.scala 71:36]
    io.macIO.weightWeDelay <= io_macIO_weightWeDelay_REG @[MAC.scala 71:26]
    node _io_macIO_weightTagDelay_T = add(io.macIO.weightTag, UInt<1>("h1")) @[MAC.scala 72:58]
    node _io_macIO_weightTagDelay_T_1 = tail(_io_macIO_weightTagDelay_T, 1) @[MAC.scala 72:58]
    reg io_macIO_weightTagDelay_REG : UInt, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 72:37]
    io_macIO_weightTagDelay_REG <= _io_macIO_weightTagDelay_T_1 @[MAC.scala 72:37]
    io.macIO.weightTagDelay <= io_macIO_weightTagDelay_REG @[MAC.scala 72:27]

  module MYMAC_4 :
    input clock : Clock
    input reset : Reset
    output io : { macIO : { flip dataIn : SInt<8>, flip accIn : SInt<32>, flip switchw : UInt<1>, flip weightIn : SInt<8>, flip weightWe : UInt<1>, flip weightTag : UInt<8>, outDelay : SInt, dataDelay : SInt, switchDelay : UInt<1>, weightDelay : SInt, weightWeDelay : UInt<1>, weightTagDelay : UInt}}

    reg wbuf1 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg wbuf2 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg currentBufferReg : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 46:33]
    when io.macIO.switchw : @[MAC.scala 47:25]
      node _currentBufferReg_T = not(currentBufferReg) @[MAC.scala 48:25]
      currentBufferReg <= _currentBufferReg_T @[MAC.scala 48:22]
    node currenBuffer = xor(currentBufferReg, io.macIO.switchw) @[MAC.scala 51:39]
    node _T = eq(io.macIO.weightTag, UInt<2>("h2")) @[MAC.scala 53:47]
    node _T_1 = and(io.macIO.weightWe, _T) @[MAC.scala 53:26]
    when _T_1 : @[MAC.scala 53:67]
      node _T_2 = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 54:22]
      when _T_2 : @[MAC.scala 54:29]
        wbuf2 <= io.macIO.weightIn @[MAC.scala 55:13]
      else :
        wbuf1 <= io.macIO.weightIn @[MAC.scala 57:13]
    node _weight_T = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 61:32]
    node weight = mux(_weight_T, wbuf2, wbuf1) @[MAC.scala 61:19]
    node product = mul(weight, io.macIO.dataIn) @[MAC.scala 62:24]
    node _out_T = add(product, io.macIO.accIn) @[MAC.scala 63:21]
    node _out_T_1 = tail(_out_T, 1) @[MAC.scala 63:21]
    node out = asSInt(_out_T_1) @[MAC.scala 63:21]
    reg io_macIO_dataDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 67:32]
    io_macIO_dataDelay_REG <= io.macIO.dataIn @[MAC.scala 67:32]
    io.macIO.dataDelay <= io_macIO_dataDelay_REG @[MAC.scala 67:22]
    reg io_macIO_switchDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 68:34]
    io_macIO_switchDelay_REG <= io.macIO.switchw @[MAC.scala 68:34]
    io.macIO.switchDelay <= io_macIO_switchDelay_REG @[MAC.scala 68:24]
    reg io_macIO_outDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 69:31]
    io_macIO_outDelay_REG <= out @[MAC.scala 69:31]
    io.macIO.outDelay <= io_macIO_outDelay_REG @[MAC.scala 69:21]
    reg io_macIO_weightDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 70:34]
    io_macIO_weightDelay_REG <= io.macIO.weightIn @[MAC.scala 70:34]
    io.macIO.weightDelay <= io_macIO_weightDelay_REG @[MAC.scala 70:24]
    reg io_macIO_weightWeDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 71:36]
    io_macIO_weightWeDelay_REG <= io.macIO.weightWe @[MAC.scala 71:36]
    io.macIO.weightWeDelay <= io_macIO_weightWeDelay_REG @[MAC.scala 71:26]
    node _io_macIO_weightTagDelay_T = add(io.macIO.weightTag, UInt<1>("h1")) @[MAC.scala 72:58]
    node _io_macIO_weightTagDelay_T_1 = tail(_io_macIO_weightTagDelay_T, 1) @[MAC.scala 72:58]
    reg io_macIO_weightTagDelay_REG : UInt, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 72:37]
    io_macIO_weightTagDelay_REG <= _io_macIO_weightTagDelay_T_1 @[MAC.scala 72:37]
    io.macIO.weightTagDelay <= io_macIO_weightTagDelay_REG @[MAC.scala 72:27]

  module MYMAC_5 :
    input clock : Clock
    input reset : Reset
    output io : { macIO : { flip dataIn : SInt<8>, flip accIn : SInt<32>, flip switchw : UInt<1>, flip weightIn : SInt<8>, flip weightWe : UInt<1>, flip weightTag : UInt<8>, outDelay : SInt, dataDelay : SInt, switchDelay : UInt<1>, weightDelay : SInt, weightWeDelay : UInt<1>, weightTagDelay : UInt}}

    reg wbuf1 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg wbuf2 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg currentBufferReg : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 46:33]
    when io.macIO.switchw : @[MAC.scala 47:25]
      node _currentBufferReg_T = not(currentBufferReg) @[MAC.scala 48:25]
      currentBufferReg <= _currentBufferReg_T @[MAC.scala 48:22]
    node currenBuffer = xor(currentBufferReg, io.macIO.switchw) @[MAC.scala 51:39]
    node _T = eq(io.macIO.weightTag, UInt<2>("h2")) @[MAC.scala 53:47]
    node _T_1 = and(io.macIO.weightWe, _T) @[MAC.scala 53:26]
    when _T_1 : @[MAC.scala 53:67]
      node _T_2 = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 54:22]
      when _T_2 : @[MAC.scala 54:29]
        wbuf2 <= io.macIO.weightIn @[MAC.scala 55:13]
      else :
        wbuf1 <= io.macIO.weightIn @[MAC.scala 57:13]
    node _weight_T = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 61:32]
    node weight = mux(_weight_T, wbuf2, wbuf1) @[MAC.scala 61:19]
    node product = mul(weight, io.macIO.dataIn) @[MAC.scala 62:24]
    node _out_T = add(product, io.macIO.accIn) @[MAC.scala 63:21]
    node _out_T_1 = tail(_out_T, 1) @[MAC.scala 63:21]
    node out = asSInt(_out_T_1) @[MAC.scala 63:21]
    reg io_macIO_dataDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 67:32]
    io_macIO_dataDelay_REG <= io.macIO.dataIn @[MAC.scala 67:32]
    io.macIO.dataDelay <= io_macIO_dataDelay_REG @[MAC.scala 67:22]
    reg io_macIO_switchDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 68:34]
    io_macIO_switchDelay_REG <= io.macIO.switchw @[MAC.scala 68:34]
    io.macIO.switchDelay <= io_macIO_switchDelay_REG @[MAC.scala 68:24]
    reg io_macIO_outDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 69:31]
    io_macIO_outDelay_REG <= out @[MAC.scala 69:31]
    io.macIO.outDelay <= io_macIO_outDelay_REG @[MAC.scala 69:21]
    reg io_macIO_weightDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 70:34]
    io_macIO_weightDelay_REG <= io.macIO.weightIn @[MAC.scala 70:34]
    io.macIO.weightDelay <= io_macIO_weightDelay_REG @[MAC.scala 70:24]
    reg io_macIO_weightWeDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 71:36]
    io_macIO_weightWeDelay_REG <= io.macIO.weightWe @[MAC.scala 71:36]
    io.macIO.weightWeDelay <= io_macIO_weightWeDelay_REG @[MAC.scala 71:26]
    node _io_macIO_weightTagDelay_T = add(io.macIO.weightTag, UInt<1>("h1")) @[MAC.scala 72:58]
    node _io_macIO_weightTagDelay_T_1 = tail(_io_macIO_weightTagDelay_T, 1) @[MAC.scala 72:58]
    reg io_macIO_weightTagDelay_REG : UInt, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 72:37]
    io_macIO_weightTagDelay_REG <= _io_macIO_weightTagDelay_T_1 @[MAC.scala 72:37]
    io.macIO.weightTagDelay <= io_macIO_weightTagDelay_REG @[MAC.scala 72:27]

  module MYMAC_6 :
    input clock : Clock
    input reset : Reset
    output io : { macIO : { flip dataIn : SInt<8>, flip accIn : SInt<32>, flip switchw : UInt<1>, flip weightIn : SInt<8>, flip weightWe : UInt<1>, flip weightTag : UInt<8>, outDelay : SInt, dataDelay : SInt, switchDelay : UInt<1>, weightDelay : SInt, weightWeDelay : UInt<1>, weightTagDelay : UInt}}

    reg wbuf1 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg wbuf2 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg currentBufferReg : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 46:33]
    when io.macIO.switchw : @[MAC.scala 47:25]
      node _currentBufferReg_T = not(currentBufferReg) @[MAC.scala 48:25]
      currentBufferReg <= _currentBufferReg_T @[MAC.scala 48:22]
    node currenBuffer = xor(currentBufferReg, io.macIO.switchw) @[MAC.scala 51:39]
    node _T = eq(io.macIO.weightTag, UInt<2>("h2")) @[MAC.scala 53:47]
    node _T_1 = and(io.macIO.weightWe, _T) @[MAC.scala 53:26]
    when _T_1 : @[MAC.scala 53:67]
      node _T_2 = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 54:22]
      when _T_2 : @[MAC.scala 54:29]
        wbuf2 <= io.macIO.weightIn @[MAC.scala 55:13]
      else :
        wbuf1 <= io.macIO.weightIn @[MAC.scala 57:13]
    node _weight_T = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 61:32]
    node weight = mux(_weight_T, wbuf2, wbuf1) @[MAC.scala 61:19]
    node product = mul(weight, io.macIO.dataIn) @[MAC.scala 62:24]
    node _out_T = add(product, io.macIO.accIn) @[MAC.scala 63:21]
    node _out_T_1 = tail(_out_T, 1) @[MAC.scala 63:21]
    node out = asSInt(_out_T_1) @[MAC.scala 63:21]
    reg io_macIO_dataDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 67:32]
    io_macIO_dataDelay_REG <= io.macIO.dataIn @[MAC.scala 67:32]
    io.macIO.dataDelay <= io_macIO_dataDelay_REG @[MAC.scala 67:22]
    reg io_macIO_switchDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 68:34]
    io_macIO_switchDelay_REG <= io.macIO.switchw @[MAC.scala 68:34]
    io.macIO.switchDelay <= io_macIO_switchDelay_REG @[MAC.scala 68:24]
    reg io_macIO_outDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 69:31]
    io_macIO_outDelay_REG <= out @[MAC.scala 69:31]
    io.macIO.outDelay <= io_macIO_outDelay_REG @[MAC.scala 69:21]
    reg io_macIO_weightDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 70:34]
    io_macIO_weightDelay_REG <= io.macIO.weightIn @[MAC.scala 70:34]
    io.macIO.weightDelay <= io_macIO_weightDelay_REG @[MAC.scala 70:24]
    reg io_macIO_weightWeDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 71:36]
    io_macIO_weightWeDelay_REG <= io.macIO.weightWe @[MAC.scala 71:36]
    io.macIO.weightWeDelay <= io_macIO_weightWeDelay_REG @[MAC.scala 71:26]
    node _io_macIO_weightTagDelay_T = add(io.macIO.weightTag, UInt<1>("h1")) @[MAC.scala 72:58]
    node _io_macIO_weightTagDelay_T_1 = tail(_io_macIO_weightTagDelay_T, 1) @[MAC.scala 72:58]
    reg io_macIO_weightTagDelay_REG : UInt, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 72:37]
    io_macIO_weightTagDelay_REG <= _io_macIO_weightTagDelay_T_1 @[MAC.scala 72:37]
    io.macIO.weightTagDelay <= io_macIO_weightTagDelay_REG @[MAC.scala 72:27]

  module MYMAC_7 :
    input clock : Clock
    input reset : Reset
    output io : { macIO : { flip dataIn : SInt<8>, flip accIn : SInt<32>, flip switchw : UInt<1>, flip weightIn : SInt<8>, flip weightWe : UInt<1>, flip weightTag : UInt<8>, outDelay : SInt, dataDelay : SInt, switchDelay : UInt<1>, weightDelay : SInt, weightWeDelay : UInt<1>, weightTagDelay : UInt}}

    reg wbuf1 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg wbuf2 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg currentBufferReg : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 46:33]
    when io.macIO.switchw : @[MAC.scala 47:25]
      node _currentBufferReg_T = not(currentBufferReg) @[MAC.scala 48:25]
      currentBufferReg <= _currentBufferReg_T @[MAC.scala 48:22]
    node currenBuffer = xor(currentBufferReg, io.macIO.switchw) @[MAC.scala 51:39]
    node _T = eq(io.macIO.weightTag, UInt<2>("h2")) @[MAC.scala 53:47]
    node _T_1 = and(io.macIO.weightWe, _T) @[MAC.scala 53:26]
    when _T_1 : @[MAC.scala 53:67]
      node _T_2 = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 54:22]
      when _T_2 : @[MAC.scala 54:29]
        wbuf2 <= io.macIO.weightIn @[MAC.scala 55:13]
      else :
        wbuf1 <= io.macIO.weightIn @[MAC.scala 57:13]
    node _weight_T = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 61:32]
    node weight = mux(_weight_T, wbuf2, wbuf1) @[MAC.scala 61:19]
    node product = mul(weight, io.macIO.dataIn) @[MAC.scala 62:24]
    node _out_T = add(product, io.macIO.accIn) @[MAC.scala 63:21]
    node _out_T_1 = tail(_out_T, 1) @[MAC.scala 63:21]
    node out = asSInt(_out_T_1) @[MAC.scala 63:21]
    reg io_macIO_dataDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 67:32]
    io_macIO_dataDelay_REG <= io.macIO.dataIn @[MAC.scala 67:32]
    io.macIO.dataDelay <= io_macIO_dataDelay_REG @[MAC.scala 67:22]
    reg io_macIO_switchDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 68:34]
    io_macIO_switchDelay_REG <= io.macIO.switchw @[MAC.scala 68:34]
    io.macIO.switchDelay <= io_macIO_switchDelay_REG @[MAC.scala 68:24]
    reg io_macIO_outDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 69:31]
    io_macIO_outDelay_REG <= out @[MAC.scala 69:31]
    io.macIO.outDelay <= io_macIO_outDelay_REG @[MAC.scala 69:21]
    reg io_macIO_weightDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 70:34]
    io_macIO_weightDelay_REG <= io.macIO.weightIn @[MAC.scala 70:34]
    io.macIO.weightDelay <= io_macIO_weightDelay_REG @[MAC.scala 70:24]
    reg io_macIO_weightWeDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 71:36]
    io_macIO_weightWeDelay_REG <= io.macIO.weightWe @[MAC.scala 71:36]
    io.macIO.weightWeDelay <= io_macIO_weightWeDelay_REG @[MAC.scala 71:26]
    node _io_macIO_weightTagDelay_T = add(io.macIO.weightTag, UInt<1>("h1")) @[MAC.scala 72:58]
    node _io_macIO_weightTagDelay_T_1 = tail(_io_macIO_weightTagDelay_T, 1) @[MAC.scala 72:58]
    reg io_macIO_weightTagDelay_REG : UInt, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 72:37]
    io_macIO_weightTagDelay_REG <= _io_macIO_weightTagDelay_T_1 @[MAC.scala 72:37]
    io.macIO.weightTagDelay <= io_macIO_weightTagDelay_REG @[MAC.scala 72:27]

  module MYMAC_8 :
    input clock : Clock
    input reset : Reset
    output io : { macIO : { flip dataIn : SInt<8>, flip accIn : SInt<32>, flip switchw : UInt<1>, flip weightIn : SInt<8>, flip weightWe : UInt<1>, flip weightTag : UInt<8>, outDelay : SInt, dataDelay : SInt, switchDelay : UInt<1>, weightDelay : SInt, weightWeDelay : UInt<1>, weightTagDelay : UInt}}

    reg wbuf1 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg wbuf2 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg currentBufferReg : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 46:33]
    when io.macIO.switchw : @[MAC.scala 47:25]
      node _currentBufferReg_T = not(currentBufferReg) @[MAC.scala 48:25]
      currentBufferReg <= _currentBufferReg_T @[MAC.scala 48:22]
    node currenBuffer = xor(currentBufferReg, io.macIO.switchw) @[MAC.scala 51:39]
    node _T = eq(io.macIO.weightTag, UInt<2>("h2")) @[MAC.scala 53:47]
    node _T_1 = and(io.macIO.weightWe, _T) @[MAC.scala 53:26]
    when _T_1 : @[MAC.scala 53:67]
      node _T_2 = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 54:22]
      when _T_2 : @[MAC.scala 54:29]
        wbuf2 <= io.macIO.weightIn @[MAC.scala 55:13]
      else :
        wbuf1 <= io.macIO.weightIn @[MAC.scala 57:13]
    node _weight_T = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 61:32]
    node weight = mux(_weight_T, wbuf2, wbuf1) @[MAC.scala 61:19]
    node product = mul(weight, io.macIO.dataIn) @[MAC.scala 62:24]
    node _out_T = add(product, io.macIO.accIn) @[MAC.scala 63:21]
    node _out_T_1 = tail(_out_T, 1) @[MAC.scala 63:21]
    node out = asSInt(_out_T_1) @[MAC.scala 63:21]
    reg io_macIO_dataDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 67:32]
    io_macIO_dataDelay_REG <= io.macIO.dataIn @[MAC.scala 67:32]
    io.macIO.dataDelay <= io_macIO_dataDelay_REG @[MAC.scala 67:22]
    reg io_macIO_switchDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 68:34]
    io_macIO_switchDelay_REG <= io.macIO.switchw @[MAC.scala 68:34]
    io.macIO.switchDelay <= io_macIO_switchDelay_REG @[MAC.scala 68:24]
    reg io_macIO_outDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 69:31]
    io_macIO_outDelay_REG <= out @[MAC.scala 69:31]
    io.macIO.outDelay <= io_macIO_outDelay_REG @[MAC.scala 69:21]
    reg io_macIO_weightDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 70:34]
    io_macIO_weightDelay_REG <= io.macIO.weightIn @[MAC.scala 70:34]
    io.macIO.weightDelay <= io_macIO_weightDelay_REG @[MAC.scala 70:24]
    reg io_macIO_weightWeDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 71:36]
    io_macIO_weightWeDelay_REG <= io.macIO.weightWe @[MAC.scala 71:36]
    io.macIO.weightWeDelay <= io_macIO_weightWeDelay_REG @[MAC.scala 71:26]
    node _io_macIO_weightTagDelay_T = add(io.macIO.weightTag, UInt<1>("h1")) @[MAC.scala 72:58]
    node _io_macIO_weightTagDelay_T_1 = tail(_io_macIO_weightTagDelay_T, 1) @[MAC.scala 72:58]
    reg io_macIO_weightTagDelay_REG : UInt, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 72:37]
    io_macIO_weightTagDelay_REG <= _io_macIO_weightTagDelay_T_1 @[MAC.scala 72:37]
    io.macIO.weightTagDelay <= io_macIO_weightTagDelay_REG @[MAC.scala 72:27]

  module MACArray :
    input clock : Clock
    input reset : Reset
    output io : { flip dataIn : SInt<8>[3], flip switchw : UInt<1>[3], flip weightIn : UInt<24>[3], flip weightWe : UInt<1>, dataOut : SInt<32>[3]}

    inst MYMAC of MYMAC @[MACArray.scala 22:15]
    MYMAC.clock <= clock
    MYMAC.reset <= reset
    inst MYMAC_1 of MYMAC_1 @[MACArray.scala 22:15]
    MYMAC_1.clock <= clock
    MYMAC_1.reset <= reset
    inst MYMAC_2 of MYMAC_2 @[MACArray.scala 22:15]
    MYMAC_2.clock <= clock
    MYMAC_2.reset <= reset
    inst MYMAC_3 of MYMAC_3 @[MACArray.scala 22:15]
    MYMAC_3.clock <= clock
    MYMAC_3.reset <= reset
    inst MYMAC_4 of MYMAC_4 @[MACArray.scala 22:15]
    MYMAC_4.clock <= clock
    MYMAC_4.reset <= reset
    inst MYMAC_5 of MYMAC_5 @[MACArray.scala 22:15]
    MYMAC_5.clock <= clock
    MYMAC_5.reset <= reset
    inst MYMAC_6 of MYMAC_6 @[MACArray.scala 22:15]
    MYMAC_6.clock <= clock
    MYMAC_6.reset <= reset
    inst MYMAC_7 of MYMAC_7 @[MACArray.scala 22:15]
    MYMAC_7.clock <= clock
    MYMAC_7.reset <= reset
    inst MYMAC_8 of MYMAC_8 @[MACArray.scala 22:15]
    MYMAC_8.clock <= clock
    MYMAC_8.reset <= reset
    wire weightWes : UInt<1>[3] @[MACArray.scala 25:25]
    reg programming : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MACArray.scala 26:30]
    reg progstep : UInt<2>, clock with :
      reset => (reset, UInt<2>("h0")) @[MACArray.scala 27:27]
    wire weightTags : UInt<2>[3] @[MACArray.scala 28:26]
    node _T = eq(programming, UInt<1>("h0")) @[MACArray.scala 31:36]
    node _T_1 = and(io.weightWe, _T) @[MACArray.scala 31:22]
    when _T_1 : @[MACArray.scala 31:48]
      programming <= UInt<1>("h1") @[MACArray.scala 32:21]
    else :
      node _T_2 = eq(programming, UInt<1>("h1")) @[MACArray.scala 33:28]
      node _T_3 = eq(progstep, UInt<2>("h2")) @[MACArray.scala 33:52]
      node _T_4 = and(_T_2, _T_3) @[MACArray.scala 33:40]
      when _T_4 : @[MACArray.scala 33:73]
        programming <= UInt<1>("h0") @[MACArray.scala 34:21]
    node _T_5 = eq(programming, UInt<1>("h1")) @[MACArray.scala 37:21]
    when _T_5 : @[MACArray.scala 37:33]
      node _progstep_T = add(progstep, UInt<1>("h1")) @[MACArray.scala 38:30]
      node _progstep_T_1 = tail(_progstep_T, 1) @[MACArray.scala 38:30]
      progstep <= _progstep_T_1 @[MACArray.scala 38:18]
    else :
      progstep <= UInt<1>("h0") @[MACArray.scala 40:18]
    weightWes[0] <= programming @[MACArray.scala 45:22]
    weightTags[0] <= progstep @[MACArray.scala 46:23]
    weightWes[1] <= programming @[MACArray.scala 45:22]
    weightTags[1] <= progstep @[MACArray.scala 46:23]
    weightWes[2] <= programming @[MACArray.scala 45:22]
    weightTags[2] <= progstep @[MACArray.scala 46:23]
    MYMAC_3.io.macIO.weightIn <= MYMAC.io.macIO.weightDelay @[MACArray.scala 59:56]
    MYMAC_3.io.macIO.weightWe <= MYMAC.io.macIO.weightWeDelay @[MACArray.scala 60:56]
    MYMAC_3.io.macIO.accIn <= MYMAC.io.macIO.outDelay @[MACArray.scala 61:53]
    MYMAC_3.io.macIO.weightTag <= MYMAC.io.macIO.weightTagDelay @[MACArray.scala 62:57]
    MYMAC_4.io.macIO.weightIn <= MYMAC_1.io.macIO.weightDelay @[MACArray.scala 59:56]
    MYMAC_4.io.macIO.weightWe <= MYMAC_1.io.macIO.weightWeDelay @[MACArray.scala 60:56]
    MYMAC_4.io.macIO.accIn <= MYMAC_1.io.macIO.outDelay @[MACArray.scala 61:53]
    MYMAC_4.io.macIO.weightTag <= MYMAC_1.io.macIO.weightTagDelay @[MACArray.scala 62:57]
    MYMAC_5.io.macIO.weightIn <= MYMAC_2.io.macIO.weightDelay @[MACArray.scala 59:56]
    MYMAC_5.io.macIO.weightWe <= MYMAC_2.io.macIO.weightWeDelay @[MACArray.scala 60:56]
    MYMAC_5.io.macIO.accIn <= MYMAC_2.io.macIO.outDelay @[MACArray.scala 61:53]
    MYMAC_5.io.macIO.weightTag <= MYMAC_2.io.macIO.weightTagDelay @[MACArray.scala 62:57]
    MYMAC_6.io.macIO.weightIn <= MYMAC_3.io.macIO.weightDelay @[MACArray.scala 59:56]
    MYMAC_6.io.macIO.weightWe <= MYMAC_3.io.macIO.weightWeDelay @[MACArray.scala 60:56]
    MYMAC_6.io.macIO.accIn <= MYMAC_3.io.macIO.outDelay @[MACArray.scala 61:53]
    MYMAC_6.io.macIO.weightTag <= MYMAC_3.io.macIO.weightTagDelay @[MACArray.scala 62:57]
    MYMAC_7.io.macIO.weightIn <= MYMAC_4.io.macIO.weightDelay @[MACArray.scala 59:56]
    MYMAC_7.io.macIO.weightWe <= MYMAC_4.io.macIO.weightWeDelay @[MACArray.scala 60:56]
    MYMAC_7.io.macIO.accIn <= MYMAC_4.io.macIO.outDelay @[MACArray.scala 61:53]
    MYMAC_7.io.macIO.weightTag <= MYMAC_4.io.macIO.weightTagDelay @[MACArray.scala 62:57]
    MYMAC_8.io.macIO.weightIn <= MYMAC_5.io.macIO.weightDelay @[MACArray.scala 59:56]
    MYMAC_8.io.macIO.weightWe <= MYMAC_5.io.macIO.weightWeDelay @[MACArray.scala 60:56]
    MYMAC_8.io.macIO.accIn <= MYMAC_5.io.macIO.outDelay @[MACArray.scala 61:53]
    MYMAC_8.io.macIO.weightTag <= MYMAC_5.io.macIO.weightTagDelay @[MACArray.scala 62:57]
    MYMAC_1.io.macIO.dataIn <= MYMAC.io.macIO.dataDelay @[MACArray.scala 69:52]
    MYMAC_1.io.macIO.switchw <= MYMAC.io.macIO.switchDelay @[MACArray.scala 70:53]
    MYMAC_2.io.macIO.dataIn <= MYMAC_1.io.macIO.dataDelay @[MACArray.scala 69:52]
    MYMAC_2.io.macIO.switchw <= MYMAC_1.io.macIO.switchDelay @[MACArray.scala 70:53]
    MYMAC_4.io.macIO.dataIn <= MYMAC_3.io.macIO.dataDelay @[MACArray.scala 69:52]
    MYMAC_4.io.macIO.switchw <= MYMAC_3.io.macIO.switchDelay @[MACArray.scala 70:53]
    MYMAC_5.io.macIO.dataIn <= MYMAC_4.io.macIO.dataDelay @[MACArray.scala 69:52]
    MYMAC_5.io.macIO.switchw <= MYMAC_4.io.macIO.switchDelay @[MACArray.scala 70:53]
    MYMAC_7.io.macIO.dataIn <= MYMAC_6.io.macIO.dataDelay @[MACArray.scala 69:52]
    MYMAC_7.io.macIO.switchw <= MYMAC_6.io.macIO.switchDelay @[MACArray.scala 70:53]
    MYMAC_8.io.macIO.dataIn <= MYMAC_7.io.macIO.dataDelay @[MACArray.scala 69:52]
    MYMAC_8.io.macIO.switchw <= MYMAC_7.io.macIO.switchDelay @[MACArray.scala 70:53]
    io.dataOut[0] <= MYMAC_6.io.macIO.outDelay @[MACArray.scala 76:23]
    io.dataOut[1] <= MYMAC_7.io.macIO.outDelay @[MACArray.scala 76:23]
    io.dataOut[2] <= MYMAC_8.io.macIO.outDelay @[MACArray.scala 76:23]
    MYMAC.io.macIO.dataIn <= io.dataIn[0] @[MACArray.scala 81:44]
    MYMAC.io.macIO.switchw <= io.switchw[0] @[MACArray.scala 82:45]
    MYMAC_3.io.macIO.dataIn <= io.dataIn[1] @[MACArray.scala 81:44]
    MYMAC_3.io.macIO.switchw <= io.switchw[1] @[MACArray.scala 82:45]
    MYMAC_6.io.macIO.dataIn <= io.dataIn[2] @[MACArray.scala 81:44]
    MYMAC_6.io.macIO.switchw <= io.switchw[2] @[MACArray.scala 82:45]
    node _T_6 = eq(UInt<2>("h2"), progstep) @[MACArray.scala 93:32]
    node _T_7 = eq(UInt<1>("h1"), progstep) @[MACArray.scala 93:32]
    node _T_8 = eq(UInt<1>("h0"), progstep) @[MACArray.scala 93:32]
    node _currentWeight_T = mux(_T_8, io.weightIn[2], UInt<24>("h0")) @[Mux.scala 101:16]
    node _currentWeight_T_1 = mux(_T_7, io.weightIn[1], _currentWeight_T) @[Mux.scala 101:16]
    node currentWeight = mux(_T_6, io.weightIn[0], _currentWeight_T_1) @[Mux.scala 101:16]
    wire rowWeightVec : UInt<8>[3] @[MACArray.scala 97:28]
    node _rowWeightVec_0_T = bits(currentWeight, 7, 0) @[MACArray.scala 99:41]
    rowWeightVec[0] <= _rowWeightVec_0_T @[MACArray.scala 99:25]
    node _rowWeightVec_1_T = bits(currentWeight, 15, 8) @[MACArray.scala 99:41]
    rowWeightVec[1] <= _rowWeightVec_1_T @[MACArray.scala 99:25]
    node _rowWeightVec_2_T = bits(currentWeight, 23, 16) @[MACArray.scala 99:41]
    rowWeightVec[2] <= _rowWeightVec_2_T @[MACArray.scala 99:25]
    MYMAC.io.macIO.accIn <= asSInt(UInt<32>("h0")) @[MACArray.scala 103:32]
    MYMAC.io.macIO.weightWe <= weightWes[0] @[MACArray.scala 104:35]
    node _T_9 = asSInt(rowWeightVec[0]) @[MACArray.scala 106:54]
    MYMAC.io.macIO.weightIn <= _T_9 @[MACArray.scala 106:35]
    MYMAC.io.macIO.weightTag <= weightTags[0] @[MACArray.scala 107:36]
    MYMAC_1.io.macIO.accIn <= asSInt(UInt<32>("h0")) @[MACArray.scala 103:32]
    MYMAC_1.io.macIO.weightWe <= weightWes[1] @[MACArray.scala 104:35]
    node _T_10 = asSInt(rowWeightVec[1]) @[MACArray.scala 106:54]
    MYMAC_1.io.macIO.weightIn <= _T_10 @[MACArray.scala 106:35]
    MYMAC_1.io.macIO.weightTag <= weightTags[1] @[MACArray.scala 107:36]
    MYMAC_2.io.macIO.accIn <= asSInt(UInt<32>("h0")) @[MACArray.scala 103:32]
    MYMAC_2.io.macIO.weightWe <= weightWes[2] @[MACArray.scala 104:35]
    node _T_11 = asSInt(rowWeightVec[2]) @[MACArray.scala 106:54]
    MYMAC_2.io.macIO.weightIn <= _T_11 @[MACArray.scala 106:35]
    MYMAC_2.io.macIO.weightTag <= weightTags[2] @[MACArray.scala 107:36]

  module MYAccumulator :
    input clock : Clock
    input reset : Reset
    output io : { accumIn : { flip waddr : UInt<8>, flip wen : UInt<1>, flip wclear : UInt<1>, flip lastvec : UInt<1>}, flip raddr : UInt<8>, flip dataIn : SInt<32>, flip accumOut : { flip waddr : UInt<8>, flip wen : UInt<1>, flip wclear : UInt<1>, flip lastvec : UInt<1>}, dataOut : SInt<32>}

    smem mem : SInt<32> [256] @[Accumulator.scala 27:30]
    when io.accumIn.wen : @[Accumulator.scala 29:29]
      when io.accumIn.wclear : @[Accumulator.scala 30:40]
        write mport MPORT = mem[io.accumIn.waddr], clock
        MPORT <= io.dataIn
      else :
        wire _WIRE : UInt @[Accumulator.scala 33:73]
        _WIRE is invalid @[Accumulator.scala 33:73]
        when UInt<1>("h1") : @[Accumulator.scala 33:73]
          _WIRE <= io.accumIn.waddr @[Accumulator.scala 33:73]
          node _T = or(_WIRE, UInt<8>("h0")) @[Accumulator.scala 33:73]
          node _T_1 = bits(_T, 7, 0) @[Accumulator.scala 33:73]
          read mport MPORT_1 = mem[_T_1], clock @[Accumulator.scala 33:73]
        node _T_2 = add(io.dataIn, MPORT_1) @[Accumulator.scala 33:63]
        node _T_3 = tail(_T_2, 1) @[Accumulator.scala 33:63]
        node _T_4 = asSInt(_T_3) @[Accumulator.scala 33:63]
        write mport MPORT_2 = mem[io.accumIn.waddr], clock
        MPORT_2 <= _T_4
    wire _io_dataOut_WIRE : UInt @[Accumulator.scala 37:31]
    _io_dataOut_WIRE is invalid @[Accumulator.scala 37:31]
    when UInt<1>("h1") : @[Accumulator.scala 37:31]
      _io_dataOut_WIRE <= io.raddr @[Accumulator.scala 37:31]
      node _io_dataOut_T = or(_io_dataOut_WIRE, UInt<8>("h0")) @[Accumulator.scala 37:31]
      node _io_dataOut_T_1 = bits(_io_dataOut_T, 7, 0) @[Accumulator.scala 37:31]
      read mport io_dataOut_MPORT = mem[_io_dataOut_T_1], clock @[Accumulator.scala 37:31]
    io.dataOut <= io_dataOut_MPORT @[Accumulator.scala 37:20]
    reg io_accumOut_waddr_REG : UInt, clock with :
      reset => (reset, UInt<1>("h0")) @[Accumulator.scala 39:37]
    io_accumOut_waddr_REG <= io.accumIn.waddr @[Accumulator.scala 39:37]
    io.accumOut.waddr <= io_accumOut_waddr_REG @[Accumulator.scala 39:27]
    reg io_accumOut_wen_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Accumulator.scala 40:37]
    io_accumOut_wen_REG <= io.accumIn.wen @[Accumulator.scala 40:37]
    io.accumOut.wen <= io_accumOut_wen_REG @[Accumulator.scala 40:27]
    reg io_accumOut_wclear_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Accumulator.scala 41:37]
    io_accumOut_wclear_REG <= io.accumIn.wclear @[Accumulator.scala 41:37]
    io.accumOut.wclear <= io_accumOut_wclear_REG @[Accumulator.scala 41:27]
    reg io_accumOut_lastvec_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Accumulator.scala 42:38]
    io_accumOut_lastvec_REG <= io.accumIn.lastvec @[Accumulator.scala 42:38]
    io.accumOut.lastvec <= io_accumOut_lastvec_REG @[Accumulator.scala 42:28]

  module MYAccumulator_1 :
    input clock : Clock
    input reset : Reset
    output io : { accumIn : { flip waddr : UInt<8>, flip wen : UInt<1>, flip wclear : UInt<1>, flip lastvec : UInt<1>}, flip raddr : UInt<8>, flip dataIn : SInt<32>, flip accumOut : { flip waddr : UInt<8>, flip wen : UInt<1>, flip wclear : UInt<1>, flip lastvec : UInt<1>}, dataOut : SInt<32>}

    smem mem : SInt<32> [256] @[Accumulator.scala 27:30]
    when io.accumIn.wen : @[Accumulator.scala 29:29]
      when io.accumIn.wclear : @[Accumulator.scala 30:40]
        write mport MPORT = mem[io.accumIn.waddr], clock
        MPORT <= io.dataIn
      else :
        wire _WIRE : UInt @[Accumulator.scala 33:73]
        _WIRE is invalid @[Accumulator.scala 33:73]
        when UInt<1>("h1") : @[Accumulator.scala 33:73]
          _WIRE <= io.accumIn.waddr @[Accumulator.scala 33:73]
          node _T = or(_WIRE, UInt<8>("h0")) @[Accumulator.scala 33:73]
          node _T_1 = bits(_T, 7, 0) @[Accumulator.scala 33:73]
          read mport MPORT_1 = mem[_T_1], clock @[Accumulator.scala 33:73]
        node _T_2 = add(io.dataIn, MPORT_1) @[Accumulator.scala 33:63]
        node _T_3 = tail(_T_2, 1) @[Accumulator.scala 33:63]
        node _T_4 = asSInt(_T_3) @[Accumulator.scala 33:63]
        write mport MPORT_2 = mem[io.accumIn.waddr], clock
        MPORT_2 <= _T_4
    wire _io_dataOut_WIRE : UInt @[Accumulator.scala 37:31]
    _io_dataOut_WIRE is invalid @[Accumulator.scala 37:31]
    when UInt<1>("h1") : @[Accumulator.scala 37:31]
      _io_dataOut_WIRE <= io.raddr @[Accumulator.scala 37:31]
      node _io_dataOut_T = or(_io_dataOut_WIRE, UInt<8>("h0")) @[Accumulator.scala 37:31]
      node _io_dataOut_T_1 = bits(_io_dataOut_T, 7, 0) @[Accumulator.scala 37:31]
      read mport io_dataOut_MPORT = mem[_io_dataOut_T_1], clock @[Accumulator.scala 37:31]
    io.dataOut <= io_dataOut_MPORT @[Accumulator.scala 37:20]
    reg io_accumOut_waddr_REG : UInt, clock with :
      reset => (reset, UInt<1>("h0")) @[Accumulator.scala 39:37]
    io_accumOut_waddr_REG <= io.accumIn.waddr @[Accumulator.scala 39:37]
    io.accumOut.waddr <= io_accumOut_waddr_REG @[Accumulator.scala 39:27]
    reg io_accumOut_wen_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Accumulator.scala 40:37]
    io_accumOut_wen_REG <= io.accumIn.wen @[Accumulator.scala 40:37]
    io.accumOut.wen <= io_accumOut_wen_REG @[Accumulator.scala 40:27]
    reg io_accumOut_wclear_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Accumulator.scala 41:37]
    io_accumOut_wclear_REG <= io.accumIn.wclear @[Accumulator.scala 41:37]
    io.accumOut.wclear <= io_accumOut_wclear_REG @[Accumulator.scala 41:27]
    reg io_accumOut_lastvec_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Accumulator.scala 42:38]
    io_accumOut_lastvec_REG <= io.accumIn.lastvec @[Accumulator.scala 42:38]
    io.accumOut.lastvec <= io_accumOut_lastvec_REG @[Accumulator.scala 42:28]

  module MYAccumulator_2 :
    input clock : Clock
    input reset : Reset
    output io : { accumIn : { flip waddr : UInt<8>, flip wen : UInt<1>, flip wclear : UInt<1>, flip lastvec : UInt<1>}, flip raddr : UInt<8>, flip dataIn : SInt<32>, flip accumOut : { flip waddr : UInt<8>, flip wen : UInt<1>, flip wclear : UInt<1>, flip lastvec : UInt<1>}, dataOut : SInt<32>}

    smem mem : SInt<32> [256] @[Accumulator.scala 27:30]
    when io.accumIn.wen : @[Accumulator.scala 29:29]
      when io.accumIn.wclear : @[Accumulator.scala 30:40]
        write mport MPORT = mem[io.accumIn.waddr], clock
        MPORT <= io.dataIn
      else :
        wire _WIRE : UInt @[Accumulator.scala 33:73]
        _WIRE is invalid @[Accumulator.scala 33:73]
        when UInt<1>("h1") : @[Accumulator.scala 33:73]
          _WIRE <= io.accumIn.waddr @[Accumulator.scala 33:73]
          node _T = or(_WIRE, UInt<8>("h0")) @[Accumulator.scala 33:73]
          node _T_1 = bits(_T, 7, 0) @[Accumulator.scala 33:73]
          read mport MPORT_1 = mem[_T_1], clock @[Accumulator.scala 33:73]
        node _T_2 = add(io.dataIn, MPORT_1) @[Accumulator.scala 33:63]
        node _T_3 = tail(_T_2, 1) @[Accumulator.scala 33:63]
        node _T_4 = asSInt(_T_3) @[Accumulator.scala 33:63]
        write mport MPORT_2 = mem[io.accumIn.waddr], clock
        MPORT_2 <= _T_4
    wire _io_dataOut_WIRE : UInt @[Accumulator.scala 37:31]
    _io_dataOut_WIRE is invalid @[Accumulator.scala 37:31]
    when UInt<1>("h1") : @[Accumulator.scala 37:31]
      _io_dataOut_WIRE <= io.raddr @[Accumulator.scala 37:31]
      node _io_dataOut_T = or(_io_dataOut_WIRE, UInt<8>("h0")) @[Accumulator.scala 37:31]
      node _io_dataOut_T_1 = bits(_io_dataOut_T, 7, 0) @[Accumulator.scala 37:31]
      read mport io_dataOut_MPORT = mem[_io_dataOut_T_1], clock @[Accumulator.scala 37:31]
    io.dataOut <= io_dataOut_MPORT @[Accumulator.scala 37:20]
    reg io_accumOut_waddr_REG : UInt, clock with :
      reset => (reset, UInt<1>("h0")) @[Accumulator.scala 39:37]
    io_accumOut_waddr_REG <= io.accumIn.waddr @[Accumulator.scala 39:37]
    io.accumOut.waddr <= io_accumOut_waddr_REG @[Accumulator.scala 39:27]
    reg io_accumOut_wen_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Accumulator.scala 40:37]
    io_accumOut_wen_REG <= io.accumIn.wen @[Accumulator.scala 40:37]
    io.accumOut.wen <= io_accumOut_wen_REG @[Accumulator.scala 40:27]
    reg io_accumOut_wclear_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Accumulator.scala 41:37]
    io_accumOut_wclear_REG <= io.accumIn.wclear @[Accumulator.scala 41:37]
    io.accumOut.wclear <= io_accumOut_wclear_REG @[Accumulator.scala 41:27]
    reg io_accumOut_lastvec_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[Accumulator.scala 42:38]
    io_accumOut_lastvec_REG <= io.accumIn.lastvec @[Accumulator.scala 42:38]
    io.accumOut.lastvec <= io_accumOut_lastvec_REG @[Accumulator.scala 42:28]

  module MYAccumulators :
    input clock : Clock
    input reset : Reset
    output io : { accumsIn : { flip waddr : UInt<8>, flip wen : UInt<1>, flip wclear : UInt<1>, flip lastvec : UInt<1>}, flip datasIn : SInt<32>[3], flip raddr : UInt<8>, datasOut : SInt<32>[3], done : UInt<1>}

    inst MYAccumulator of MYAccumulator @[Accumulator.scala 58:23]
    MYAccumulator.clock <= clock
    MYAccumulator.reset <= reset
    inst MYAccumulator_1 of MYAccumulator_1 @[Accumulator.scala 58:23]
    MYAccumulator_1.clock <= clock
    MYAccumulator_1.reset <= reset
    inst MYAccumulator_2 of MYAccumulator_2 @[Accumulator.scala 58:23]
    MYAccumulator_2.clock <= clock
    MYAccumulator_2.reset <= reset
    MYAccumulator.io.accumIn.lastvec <= io.accumsIn.lastvec @[Accumulator.scala 65:46]
    MYAccumulator.io.accumIn.wclear <= io.accumsIn.wclear @[Accumulator.scala 65:46]
    MYAccumulator.io.accumIn.wen <= io.accumsIn.wen @[Accumulator.scala 65:46]
    MYAccumulator.io.accumIn.waddr <= io.accumsIn.waddr @[Accumulator.scala 65:46]
    MYAccumulator.io.raddr <= io.raddr @[Accumulator.scala 66:46]
    MYAccumulator.io.dataIn <= io.datasIn[0] @[Accumulator.scala 67:46]
    MYAccumulator_1.io.accumIn.lastvec <= MYAccumulator.io.accumOut.lastvec @[Accumulator.scala 69:46]
    MYAccumulator_1.io.accumIn.wclear <= MYAccumulator.io.accumOut.wclear @[Accumulator.scala 69:46]
    MYAccumulator_1.io.accumIn.wen <= MYAccumulator.io.accumOut.wen @[Accumulator.scala 69:46]
    MYAccumulator_1.io.accumIn.waddr <= MYAccumulator.io.accumOut.waddr @[Accumulator.scala 69:46]
    MYAccumulator_1.io.raddr <= io.raddr @[Accumulator.scala 70:44]
    MYAccumulator_1.io.dataIn <= io.datasIn[1] @[Accumulator.scala 71:47]
    MYAccumulator_2.io.accumIn.lastvec <= MYAccumulator_1.io.accumOut.lastvec @[Accumulator.scala 69:46]
    MYAccumulator_2.io.accumIn.wclear <= MYAccumulator_1.io.accumOut.wclear @[Accumulator.scala 69:46]
    MYAccumulator_2.io.accumIn.wen <= MYAccumulator_1.io.accumOut.wen @[Accumulator.scala 69:46]
    MYAccumulator_2.io.accumIn.waddr <= MYAccumulator_1.io.accumOut.waddr @[Accumulator.scala 69:46]
    MYAccumulator_2.io.raddr <= io.raddr @[Accumulator.scala 70:44]
    MYAccumulator_2.io.dataIn <= io.datasIn[2] @[Accumulator.scala 71:47]
    io.datasOut[0] <= MYAccumulator.io.dataOut @[Accumulator.scala 76:32]
    io.datasOut[1] <= MYAccumulator_1.io.dataOut @[Accumulator.scala 76:32]
    io.datasOut[2] <= MYAccumulator_2.io.dataOut @[Accumulator.scala 76:32]
    io.done <= MYAccumulator_2.io.accumOut.lastvec @[Accumulator.scala 79:17]

  module MyMMU :
    input clock : Clock
    input reset : UInt<1>
    output io : { flip vectorIn : UInt<72>, flip accumRaddr : UInt<8>, mmu2setup : { flip waddr : UInt<8>, flip wen : UInt<1>, flip wclear : UInt<1>, flip lastvec : UInt<1>}, flip switchW : UInt<1>, flip ddrData : UInt<512>, flip ddrValid : UInt<1>, done : UInt<1>, accOut : SInt<32>[3]}

    reg programming : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MyMMU.scala 32:34]
    wire waiting : UInt<1>
    waiting <= UInt<1>("h0")
    reg weightsWait : UInt<3>, clock with :
      reset => (reset, UInt<3>("h4")) @[MyMMU.scala 35:34]
    reg weightsCount : UInt<3>, clock with :
      reset => (reset, UInt<3>("h0")) @[MyMMU.scala 36:35]
    reg startup : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MyMMU.scala 38:30]
    startup <= UInt<1>("h1") @[MyMMU.scala 38:30]
    wire weightsWe : UInt<1>
    weightsWe <= UInt<1>("h0")
    wire doneProgramming : UInt<1>
    doneProgramming <= UInt<1>("h0")
    reg firstTile : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MyMMU.scala 41:32]
    inst myFifo of MYFIFO @[MyMMU.scala 57:28]
    myFifo.clock <= clock
    myFifo.reset <= reset
    myFifo.io.memData <= io.ddrData @[MyMMU.scala 59:27]
    myFifo.io.memValid <= io.ddrValid @[MyMMU.scala 60:28]
    myFifo.io.advance_fifo <= doneProgramming @[MyMMU.scala 61:32]
    inst macArraySetup of MACArraySetUp @[MyMMU.scala 77:35]
    macArraySetup.clock <= clock
    macArraySetup.reset <= reset
    macArraySetup.io.dataIn <= io.vectorIn @[MyMMU.scala 79:33]
    macArraySetup.io.mmu2setup.lastvec <= io.mmu2setup.lastvec @[MyMMU.scala 80:36]
    macArraySetup.io.mmu2setup.wclear <= io.mmu2setup.wclear @[MyMMU.scala 80:36]
    macArraySetup.io.mmu2setup.wen <= io.mmu2setup.wen @[MyMMU.scala 80:36]
    macArraySetup.io.mmu2setup.waddr <= io.mmu2setup.waddr @[MyMMU.scala 80:36]
    macArraySetup.io.switch <= io.switchW @[MyMMU.scala 81:33]
    inst macArray of MACArray @[MyMMU.scala 97:30]
    macArray.clock <= clock
    macArray.reset <= reset
    macArray.io.dataIn[0] <= macArraySetup.io.nextRow[0] @[MyMMU.scala 98:28]
    macArray.io.dataIn[1] <= macArraySetup.io.nextRow[1] @[MyMMU.scala 98:28]
    macArray.io.dataIn[2] <= macArraySetup.io.nextRow[2] @[MyMMU.scala 98:28]
    macArray.io.switchw[0] <= macArraySetup.io.switchOut[0] @[MyMMU.scala 99:29]
    macArray.io.switchw[1] <= macArraySetup.io.switchOut[1] @[MyMMU.scala 99:29]
    macArray.io.switchw[2] <= macArraySetup.io.switchOut[2] @[MyMMU.scala 99:29]
    macArray.io.weightIn[0] <= myFifo.io.tile[0] @[MyMMU.scala 100:30]
    macArray.io.weightIn[1] <= myFifo.io.tile[1] @[MyMMU.scala 100:30]
    macArray.io.weightIn[2] <= myFifo.io.tile[2] @[MyMMU.scala 100:30]
    macArray.io.weightWe <= weightsWe @[MyMMU.scala 101:30]
    inst accumulators of MYAccumulators @[MyMMU.scala 115:34]
    accumulators.clock <= clock
    accumulators.reset <= reset
    accumulators.io.accumsIn.lastvec <= macArraySetup.io.setup2accu.lastvec @[MyMMU.scala 117:34]
    accumulators.io.accumsIn.wclear <= macArraySetup.io.setup2accu.wclear @[MyMMU.scala 117:34]
    accumulators.io.accumsIn.wen <= macArraySetup.io.setup2accu.wen @[MyMMU.scala 117:34]
    accumulators.io.accumsIn.waddr <= macArraySetup.io.setup2accu.waddr @[MyMMU.scala 117:34]
    accumulators.io.datasIn[0] <= macArray.io.dataOut[0] @[MyMMU.scala 118:33]
    accumulators.io.datasIn[1] <= macArray.io.dataOut[1] @[MyMMU.scala 118:33]
    accumulators.io.datasIn[2] <= macArray.io.dataOut[2] @[MyMMU.scala 118:33]
    accumulators.io.raddr <= io.accumRaddr @[MyMMU.scala 119:31]
    io.done <= accumulators.io.done @[MyMMU.scala 121:17]
    io.accOut[0] <= accumulators.io.datasOut[0] @[MyMMU.scala 122:19]
    io.accOut[1] <= accumulators.io.datasOut[1] @[MyMMU.scala 122:19]
    io.accOut[2] <= accumulators.io.datasOut[2] @[MyMMU.scala 122:19]
    node _waiting_T = neq(weightsWait, UInt<3>("h4")) @[MyMMU.scala 125:32]
    waiting <= _waiting_T @[MyMMU.scala 125:17]
    node _T = not(startup) @[MyMMU.scala 127:14]
    when _T : @[MyMMU.scala 127:23]
      weightsWait <= UInt<3>("h4") @[MyMMU.scala 128:29]
    else :
      when waiting : @[MyMMU.scala 129:28]
        node _weightsWait_T = add(weightsWait, UInt<1>("h1")) @[MyMMU.scala 130:44]
        node _weightsWait_T_1 = tail(_weightsWait_T, 1) @[MyMMU.scala 130:44]
        weightsWait <= _weightsWait_T_1 @[MyMMU.scala 130:29]
      else :
        node _T_1 = not(firstTile) @[MyMMU.scala 131:20]
        node _T_2 = and(_T_1, myFifo.io.ready) @[MyMMU.scala 131:31]
        when _T_2 : @[MyMMU.scala 131:50]
          weightsWait <= UInt<3>("h4") @[MyMMU.scala 132:29]
          programming <= UInt<1>("h1") @[MyMMU.scala 133:29]
          weightsCount <= UInt<1>("h0") @[MyMMU.scala 134:30]
          firstTile <= UInt<1>("h1") @[MyMMU.scala 135:29]
        else :
          when macArraySetup.io.switchOut[0] : @[MyMMU.scala 136:50]
            weightsWait <= UInt<1>("h0") @[MyMMU.scala 137:29]
            programming <= UInt<1>("h1") @[MyMMU.scala 138:29]
            weightsCount <= UInt<1>("h0") @[MyMMU.scala 139:30]
          else :
            when programming : @[MyMMU.scala 140:32]
              node _T_3 = eq(weightsCount, UInt<2>("h2")) @[MyMMU.scala 141:34]
              when _T_3 : @[MyMMU.scala 141:54]
                programming <= UInt<1>("h0") @[MyMMU.scala 142:37]
                doneProgramming <= UInt<1>("h1") @[MyMMU.scala 143:41]
              else :
                node _weightsCount_T = add(weightsCount, UInt<1>("h1")) @[MyMMU.scala 145:54]
                node _weightsCount_T_1 = tail(_weightsCount_T, 1) @[MyMMU.scala 145:54]
                weightsCount <= _weightsCount_T_1 @[MyMMU.scala 145:38]
                weightsWe <= UInt<1>("h1") @[MyMMU.scala 146:35]

